JPH0414951Y2 - - Google Patents

Info

Publication number
JPH0414951Y2
JPH0414951Y2 JP1985153440U JP15344085U JPH0414951Y2 JP H0414951 Y2 JPH0414951 Y2 JP H0414951Y2 JP 1985153440 U JP1985153440 U JP 1985153440U JP 15344085 U JP15344085 U JP 15344085U JP H0414951 Y2 JPH0414951 Y2 JP H0414951Y2
Authority
JP
Japan
Prior art keywords
printed wiring
wiring board
layer confirmation
layer
multilayer printed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1985153440U
Other languages
English (en)
Japanese (ja)
Other versions
JPS6262477U (en]
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1985153440U priority Critical patent/JPH0414951Y2/ja
Publication of JPS6262477U publication Critical patent/JPS6262477U/ja
Application granted granted Critical
Publication of JPH0414951Y2 publication Critical patent/JPH0414951Y2/ja
Expired legal-status Critical Current

Links

Landscapes

  • Structure Of Printed Boards (AREA)
JP1985153440U 1985-10-07 1985-10-07 Expired JPH0414951Y2 (en])

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1985153440U JPH0414951Y2 (en]) 1985-10-07 1985-10-07

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1985153440U JPH0414951Y2 (en]) 1985-10-07 1985-10-07

Publications (2)

Publication Number Publication Date
JPS6262477U JPS6262477U (en]) 1987-04-17
JPH0414951Y2 true JPH0414951Y2 (en]) 1992-04-03

Family

ID=31072323

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1985153440U Expired JPH0414951Y2 (en]) 1985-10-07 1985-10-07

Country Status (1)

Country Link
JP (1) JPH0414951Y2 (en])

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5516478A (en) * 1978-07-21 1980-02-05 Atsushi Okazaki Internal stop ball sealing structure
JPS5920825B2 (ja) * 1978-10-03 1984-05-15 鹿島建設株式会社 ケ−ソン工事システム
JPS5553490A (en) * 1978-10-16 1980-04-18 Fujitsu Ltd Method of manufacturing multilayer printed circuit board
JPS5583295A (en) * 1978-12-20 1980-06-23 Fujitsu Ltd Method of fabricating multilayer printed board
JPS59104559U (ja) * 1982-12-29 1984-07-13 富士通株式会社 基準パタ−ン入り多層プリント基板
JPH0341490Y2 (en]) * 1985-08-28 1991-08-30

Also Published As

Publication number Publication date
JPS6262477U (en]) 1987-04-17

Similar Documents

Publication Publication Date Title
EP2079292A3 (en) Manufacturing method of multilayer substrate and multilayer substrate produced by the manufacturing method
JPH06349372A (ja) 電気的膜パネルの製造方法
CN103327756A (zh) 具有局部混合结构的多层电路板及其制作方法
JPS58180094A (ja) 多層プリント配線板の製造方法
JPH10163630A (ja) 多層印刷回路基盤及びその製造方法
US20070167056A1 (en) Multi-layer printed circuit board, and method for detecting errors in laminating order of layers thereof
JPH0414951Y2 (en])
JP2000340950A (ja) 多層回路基板における積層合致精度検査マーク構造
JP2638555B2 (ja) 多層プリント配線板
JPH01298796A (ja) 混成集積回路
CN113645748A (zh) 可弯折电路板及其制作方法
JPH1056272A (ja) 多層プリント配線板
JPH08330743A (ja) 多層プリント配線板
JPH03250789A (ja) 多層プリント配線板
JPH0621657A (ja) 多層プリント配線板の層編成チェック用パターン
JP5104874B2 (ja) 積層順序検査方法および配線板製造方法
JPH1154945A (ja) 多層プリント配線板
JPS61168293A (ja) 多層配線基板
JPS61117889A (ja) 多層セラミツク基板
JP2989103B2 (ja) 多層プリント配線板の製造方法
JPS6263493A (ja) 多層セラミツク基板
JPH10163631A (ja) 多層印刷回路基盤及びその製造方法
JPH0526785Y2 (en])
JPH0832241A (ja) セラミック多層基板に形設される抵抗素子及びその形成方法
JPH04101497A (ja) 内層材製造用フィルム及び該フィルムを使用した多層プリント配線板の製造方法